Over the last several years, digital controllers have come into use for controlling the operation of power converters (e.g., DC/DC converters, cycloconverters, inverters and synchronous rectifiers). Like their analog predecessors, digital controllers form a part of a compensation loop that senses converter operating conditions and produces a pulse-width modulated (PWM) drive signal that controls the operation of one or more power switches in the power converter based on the converter operating conditions. Although suitable for a wide variety of processors, digital controllers are frequently embodied in digital signal processors (DSPs), which are well known to those skilled in the pertinent art.
Many digital controller topologies use a counter that counts up or down to define the PWM drive signal switching interval or period (defined as a full 360° “on-off” switching cycle and typically held constant) and duty cycle (defined as the percentage of that switching cycle during which the switch is “on,” which changes based on converter operating conditions). The same clock that drives the DSP drives the counter. For this reason, both the switching interval and the duty cycle are conveniently expressed in terms of clock cycles.
For example, if a counter is to generate a 100 KHz switching interval and is driven by a 10 MHz clock, 100 clock cycles (10×109/100×106) define the switching interval, and the duty cycle can assume integer values between 0 and 100 clock cycles. (As a practical matter, however, good controller design recommends maintaining the duty cycle at around 50%, or 50 clock cycles in the given example, under nominal converter operating conditions.) The result is that 100 discrete pulse widths are possible, each of which are 0.1 μS apart. Given a duty cycle of 50%, the pulse width of the PWM drive signal is 5 μS, resulting in a resolution of 2% (0.1 μS/5 μS).
Continuing the above example, the converter controller may determine that a duty cycle of 50.5% is required to produce a desired 48.48 volt converter output. Unfortunately, as is readily apparent, only integer duty cycles are possible; resolution below 2% is unattainable. Therefore, conventional converter controllers are forced to select a duty cycle of either 50% or 51%. Consequently, the power converter produces an output voltage that is either lower or higher than the desired 48.48V. The converter controller will respond to this suboptimal operating condition by vacillating between 50% and 51% duty cycles in an unpredictable fashion. The result is that a 2% ripple is created in the converter output voltage. Unfortunately, due to the nature of the compensation loop, this ripple is of relatively low frequency (on the order of perhaps several kilohertz) and aperiodic. The 2% ripple translates to 960 mV if the desired output voltage is 48.48V. Not only does this amount of ripple fail most power converter requirements, its relatively low and varying frequency makes filtering quite difficult.
A simple solution to this problem would be to double the clock rate to accommodate a 50.5% duty cycle. However, faster clocks and DSPs are more expensive and consume more power. Furthermore, a faster DSP may only temporarily satisfy the need for higher resolution PWM drive signals: today's “high resolution” PWM signal may be tomorrow's “low resolution” PWM signal. Thus, even with faster DSPs, the need for increasing the resolution of PWM signals without increasing the clock rate still acutely exists.
What is needed in the art is a way to improve PWM signal resolution in a digital converter controller without requiring a faster clock.